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1 ? fn8105.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. x28c010, x28ht010 5v, byte alterable eeprom the intersil x28c010/x28ht010 is a 128k x 8 eeprom, fabricated with intersil's proprietary, high performance, floating gate cmos technol ogy. like all intersil programmable non-volatile memories, the x28c010/x28ht010 is a 5v only device. the x28c010/x28ht010 features the jedec approved pin out for byte-wide memories, compatible with industry standard eeproms. the x28c010/x28ht010 supports a 256-byte page write operation, effectively providi ng a 19s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. the x28c0 10/x28ht010 also features data polling and toggle bit polling, system software support schemes used to indicate the early completion of a write cycle. in addition, th e x28c010/x28ht010 supports software data protection option. intersil eeproms are designed and tested for applications requiring extended endurance. da ta retention is specified to be greater than 100 years. features ? access time: 120ns ? simple byte and page write - single 5v supply - no external high voltages or v pp control circuits - self-timed ? no erase before write ? no complex programming algorithms ? no overerase problem ? low power cmos - active: 50ma - standby: 500a ? software data protection - protects data against system level inadvertent writes ? high speed page write capability ? highly reliable direct write ? cell - endurance: 100,000 write cycles - data retention: 100 years ? early end of write detection -data polling - toggle bit polling ? x28ht010 is fuly functional @ +175c pinouts nc a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28c010 cerdip flat pack soic (r) pga x28c010 (bottom view) 14 a 0 16 i/o 1 18 v ss 11 a 3 9 a 5 7 a 7 15 i/o 0 17 i/o 2 19 i/o 3 5 a 15 2 nc 36 v cc 20 i/o 4 21 i/o 5 34 nc 23 i/o 7 25 a 10 27 a 11 29 a 8 22 i/o 6 32 nc 24 ce 26 oe 28 a 9 30 a 13 13 a 1 12 a 2 10 a 4 8 a 6 4 a 16 3 nc 1 nc 35 we 33 nc 31 a 14 6 a 12 x28c010 (top view) a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 a 13 a 8 a 9 a 11 a 10 i/o 7 a 14 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 a 12 a 15 a 16 nc v cc we nc oe ce a 7 30 extended lcc 22 23 24 25 26 27 28 29 21 6 5 8 7 9 10 11 12 13 232 43 31 1 15 17 16 18 19 20 14 data sheet february 12, 2007
2 fn8105.1 february 12, 2007 ordering information part number part marking access time temp range (c) package pkg. dwg # x28c010d-12 x28c010d-12 120ns 0 to +70 32-ld cerdip f32.6 x28c010d-15 x28c010d-15 150ns 0 to +70 32-ld cerdip f32.6 x28c010di x28c010di - -40 to +85 32-ld cerdip f32.6 x28c010di-12 x28c010di-12 120ns -40 to +85 32-ld cerdip f32.6 x28c010di-15 x28c010di-15 150ns -40 to +85 32-ld cerdip f32.6 x28c010dm x28c010dm - -55 to +125 32-ld cerdip f32.6 x28c010dm-12 x28c010dm-12 120ns -55 to +125 32-ld cerdip f32.6 x28c010dm-15 x28c010dm-15 150ns -55 to +125 32-ld cerdip f32.6 x28c010dmb-12 c x28c010dmb-12 120ns mil-std-883 32-ld cerdip f32.6 x28c010dmb-15 c x28c010dmb-15 150ns mil-std-883 32-ld cerdip f32.6 x28c010dmb-20 c x28c010dmb-20 200ns mil-std-883 32-ld cerdip x28c010fi-12 x28c010fi-12 120ns -40 to +85 32-ld flat pack x28c010fi-15 x28c010fi-15 150ns -40 to +85 32-ld flat pack x28c010fi-20 x28c010fi-20 200ns -40 to +85 32-ld flat pack x28c010fm x28c010fm - -55 to +125 32-ld flat pack x28c010fm-12 x28c010fm-12 120ns -55 to +125 32-ld flat pack x28c010fmb-12 c x28c010fmb-12 120ns mil-std-883 32-ld flat pack x28c010fmb-15 c x28c010fmb-15 150ns mil-std-883 32-ld flat pack x28c010k-25 x28c010k-25 250ns 0 to +70 36-ld pin grid array g36.760x760a x28c010km-12 x28c010km-12 120ns -55 to +125 36-ld pin grid array g36.760x760a x28c010km-25 x28c010km-25 250ns -55 to +125 36-ld pin grid array g36.760x760a x28c010kmb-12 c x28c010kmb-12 120ns mil-std-883 36-ld pin grid array g36.760x760a x28c010kmb-15 c x28c010kmb-15 150ns mil-std-883 36-ld pin grid array g36.760x760a x28c010nm-12 x28c010nm-12 120ns -55 to +125 32-ld extended lcc x28c010nm-15 x28c010nm-15 150ns -55 to +125 32-ld extended lcc x28c010nmb-12 c x28c010nmb-12 120ns mil-std-883 32-ld extended lcc x28c010nmb-15 c x28c010nmb-15 150ns mil-std-883 32-ld extended lcc x28c010ri-12 x28c010ri-12 120ns -40 to +85 32-ld ceramic soic (gull wing) x28c010ri-20 x28c010ri-20 200ns -40 to +85 32-ld ceramic soic (gull wing) x28c010ri-20t1 x28c010ri-20 200ns -40 to +85 32-ld ceramic soic (gull wing) x28c010rm-15 x28c010rm-15 150ns -55 to +125 32-ld ceramic soic (gull wing) x28c010rmb-25 c x28c010rmb-25 250ns mil-std-883 32-ld ceramic soic (gull wing) x28ht010w 200ns -40 to +175 wafer x28c010, x28ht010
3 fn8105.1 february 12, 2007 block diagram pin descriptions addresses (a 0 -a 16 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power consumption is reduced. output enable (oe ) the output enable input controls the data output buffers, and is used to initiate read operations. data in/data out (i/o 0 -i/o 7 ) data is written to or read from the x28c010/x28ht010 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the x28c010/x28ht010. back bias voltage (v bb ) (x28ht010 only) it is required to provide -3v on pin 1. this negative voltage improves higher temper ature functionality. device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control architecture eliminates bus contention in a system environm ent. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28c010/x28ht010 supports both a ce and we controlled write cycl e. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 5ms. x buffers latches and decoder i/o buffers and latches y buffers decoder control logic and timing 1mbit eeprom array i/o 0 -i/o 7 data inputs/outputs ce oe v cc v ss we a 0 -a 7 latches and a 8 -a 16 pin names symbol description a 0 -a 16 address inputs i/o 0 -i/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect v bb *-3v *v bb applies to x28ht010 only. x28c010, x28ht010
4 fn8105.1 february 12, 2007 page write operation the page write feature of th e x28c010/x28ht010 allows the entire memory to be written in 5 seconds. page write allows two to two hundred fifty-six bytes of data to be consecutively written to the x28c010/x28ht010 prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 8 through a 16 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following th e initial byte writ e cycle, the host can write an additional one to two hundred fifty six bytes in the same manner as the first byte was written. each successive byte load cycle, started by the we high to low transition, must begin within 100s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100s, the inte rnal automatic programming cycle will commence. there is no page write window limitation. effectively the page wr ite window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. write operation status bits the x28c010/x28ht010 prov ides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. data polling (i/o 7 ) the x28c010/x28ht010 features data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a simple bit test operation to determine the status of the x28c010/x28ht010, eliminating additional interrupt inputs or external hardware. during the internal pr ogramming cycle, any attempt to read the last byte written will produce the complement of that data on i/o 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. note: if the x28c010/x28ht010 is in the prot ected state, and an illegal write operation is attempted, data polling will not operate. toggle bit (i/o 6 ) the x28c010/x28ht010 also provides another method for determining when the internal write cycle is complete. during the internal programming cycle, i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. data polling i/o 7 5 tb dp 43210 i/o reserved toggle bit data polling figure 1. status bit assignment ce oe we i/o 7 x28c010 last write high z v ol v ih a 0 -a 14 a n a n a n a n a n a n v oh a n ready figure 2. data polling bus sequence x28c010, x28ht010
5 fn8105.1 february 12, 2007 data polling can effectively halve the time for writing to the x28c010/x28ht010. the timing diagram in figure 2 illustrates the sequence of events on the bus. the software flow diagram in figure 3 illustrates one method of implementing the routine. the toggle bit i/o 6 write data save last data and address read last address io 7 compare? no yes no yes writes complete? ready x28c010 figure 3. data polling software flow ce oe we i/o 6 x28c010 v oh v ol last write high z * beginning and ending state of i/o 6 will vary * * ready figure 4. toggle bit bus sequence x28c010, x28ht010
6 fn8105.1 february 12, 2007 the toggle bit can eliminate the software housekeeping chore of saving and fetchi ng the last address and data written to a device in order to implement data polling. this can be especially helpful in an array comprised of multiple x28c010/x28ht010 memories that is frequently updated. toggle bit polling can also provide a method for status checking in multiprocessor applications. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software flow diagram in figure 5 illustrates a method for polling the toggle bit. hardware data protection the x28c010/x28ht010 provides three hardware features that protect nonvolatile data from inadvertent writes. ? noise protection?a we pulse less than 10ns will not initiate a write cycle. ? default v cc sense?all functions are inhibited when v cc is 3.5v. ? write inhibit?holding either oe low, we high, or ce high will prevent an inadve rtent write cycle during power- up and power-down, maintaining data integrity. software data protection the x28c010/x28ht010 offers a software controlled data protection feature. the x28c 010/x28ht010 is shipped from intersil with the software data protection not enabled: that is the device will be in the standard operating mode. in this mode data should be protected during power-up/-down operations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28c010/x28ht010 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28c010/x28ht010 is also prot ected from inadvertent and accidental writes in the pow ered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. refer to figures 6 and 7 for the sequence. the three byte sequence opens the page write window enab ling the host to write from one to two hundred fifty-six bytes of data. once the page load cycle has been comp leted, the device will automatically be returned to the data protected state. load accum from addr n compare accum with addr n ready no yes last write compare ok? figure 5. toggle bit software flow x28c010, x28ht010
7 fn8105.1 february 12, 2007 software data protection regardless of whether the device has previously been protected or not, once the soft ware data protection algorithm is used and data has been wr itten, the x28c010/x28ht010 will automatically disable fu rther writes unless another command is issued to cancel it. if no further commands are issued the x28c010/x28ht 010 will be write protected during power-down and after any subsequent power-up. the state of a 15 and a 16 while executing the algorithm is don?t care. note: once initiated, the sequence of write operations should not be interrupted. ce we (v cc ) write protected v cc 0v data addr aa 5555 55 2aaa a0 5555 t blc max writes ok byte or page t wc figure 6. timing sequence?byte or page write write last byte last address write data 55 to address 2aaa write data a0 to address 5555 write data xx to any address after t wc re-enters data protected state write data aa to address 5555 byte/page load operation optional figure 7. write sequence for software data protection x28c010, x28ht010
8 fn8105.1 february 12, 2007 resetting software data protection in the event the user wants to deactivate the software data protection feature for test ing or reprogramming in an eeprom programmer, the following six step algorithm will reset the internal protec tion circuit. after t wc , the x28c010/x28ht010 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. system considerations because the x28c010/x28ht010 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipation and eliminate the possibility of cont ention where multiple i/o pins share the same bus. to gain the most benefit, it is recommended that ce be decoded from the address bus and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. because the x28c010/x28ht010 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of th e i/os. therefor e, the larger the array sharing a common bu s, the larger the transient spikes. the voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capaci tors. as a minimum, it is recommended that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended th at a 4.7f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. ce we standard operating mode v cc data addr aa 5555 55 2aaa 80 5555 t wc aa 5555 55 2aaa 20 5555 figure 8. reset software data protection timing sequence write data 55 to address 2aaa write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555 figure 9. software sequence to deactivate software data protection x28c010, x28ht010
9 fn8105.1 february 12, 2007 active supply current vs. ambient temperature standby supply current vs. ambient temperature i cc (rd) by temperature over frequency -55 -10 +125 12 14 16 18 ambient temperature (c) i cc wr (ma) 10 +35 +80 v cc = 5v -55 -10 +125 0.15 0.2 0.25 0.3 ambient temperature (c) i sb (ma) 0.05 +35 +80 v cc = 5v 0.1 03 15 30 40 50 5.0 v cc frequency (mhz) i cc rd (ma) 10 69 -55c +25c 12 20 60 +125c x28c010, x28ht010
10 fn8105.1 february 12, 2007 absolute maximum ratings recommended operating conditions temperature under bias x28c010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +85c x28c010i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +135c x28c010m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +135c x28ht010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +175c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . . . -1v to +7v d.c. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300c commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c tp +85c military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 10% high temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +175c caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device at these or any other conditions (above those indicate d in the operational sections of this specification) is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical specifications over the recommended operating conditi ons, unless otherwise specified. symbol parameter test conditions min max unit i cc v cc current (active) (ttl inputs) ce = oe = v il , we = v ih , all i/o?s = open, address inputs = 0.4v/2.4v levels @ f = 5mhz 50 ma i sb1 v cc current (standby) (ttl inputs) ce = v ih , oe = v il , all i/o?s = open, other inputs = v ih 3ma i sb2 v cc current (standby) (cmos inputs) ce = v cc - 0.3v, oe = v il , all i/o?s = open, other inputs = v cc 500 a i li input leakage current v in = v ss to v cc 10 a v in = v ss to v cc (note 2) 20 a i lo output leakage current v out = v ss to v cc , ce = v ih 10 a v out = v ss to v cc , ce = v ih (note 2) 20 a v ll (note 1) input low voltage -1 0.8 v (note 2) -1 0.6 v v ih (note 1) input high voltage 2v cc + 1 v (note 2) 2.2 v cc + 1 v v ol output low voltage i ol = 2.1ma 0.4 v i ol = 1ma (note 2) 0.5 v v oh output high voltage i oh = -400a 2.4 v i oh = -400a 2.6 v i bb back bias current v bb = -3v 10% (note 2) 200 a note: 1. v il min. and v ih max. are for reference only and are not tested. 2. x28ht010w power-up timing symbol parameter max unit t pur (note 3) power-up to read operation 100 s t puw (note 3) power-up to write operation 5 ms capacitance t a = +25c, f = 1mhz, v cc = 5v symbol parameter test conditions max unit c i/o (note 3) input/output capacitance v i/o = 0v 10 pf c in (note 3) input capacitance v in = 0v 10 pf note: 3. this parameter is periodically sampled and not 100% tested. x28c010, x28ht010
11 fn8105.1 february 12, 2007 equivalent a.c. load circuit symbol table endurance and data retention parameter min max unit endurance 10,000 cycles per byte endurance 100,000 cycles per page data retention 100 years a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v mode selection ce oe we mode i/o power llh read d out active lhl write d in active h x x standby and write inhibit high z standby x l x write inhibit ? ? x x h write inhibit ? ? 5v 1.92k 100pf output 1.37k waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ac electrical specifications over the recommended operating conditi ons, unless otherwise specified. symbol parameter x28c010-12 x28c010-15 x28c010-20, x28ht010w x28c010-25 unit min max min max min max min max read cycle limits t rc read cycle time 120 150 200 250 ns t ce chip enable access time 120 150 200 250 ns t aa address access time 120 150 200 250 ns t oe output enable access time 50 50 50 50 ns t lz (note 4) ce low to active output 0 0 0 0 ns t olz (note 4) oe low to active output 0 0 0 0 ns t hz (note 4) ce high to high z output 50 50 50 50 ns t ohz (note 4) oe high to high z output 50 50 50 50 ns t oh output hold from address change 0 0 0 0 ns x28c010, x28ht010
12 fn8105.1 february 12, 2007 read cycle note: 4. t lz min.,t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf, from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid write cycle limits symbol parameter min max unit t wc (note 5) write cycle time 10 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 100 ns t oes oe high setup time 10 ns t oeh oe high hold time 10 ns t wp we pulse width 100 ns t wph we high recovery 100 ns t dv data valid 1s t ds data setup 50 ns t dh data hold 0 ns t dw delay to next write 10 s t blc byte load cycle 0.2 100 s x28c010, x28ht010
13 fn8105.1 february 12, 2007 we controlled write cycle note: 5. t wc is the minimum cycle time to be allowed from the system perspective unless po lling techniques are used. it is the maximum time the device requires to complete internal write operation. ce controlled write cycle address t as t wc t ah t oes t dv t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp t wph address t as t oeh t wc t ah t oes t wph t cs t dv t ds t dh t ch ce we oe data in data out high z data valid t cw x28c010, x28ht010
14 fn8105.1 february 12, 2007 page write cycle notes: 6. between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. 7. the timings shown above are unique to page write operations. indi vidual byte load operations within the page write must confo rm to either the ce or we controlled write cycle timing. data polling timing diagram (note 8) we oe (note 5) last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address* (note 7) i/o *for each successive write within the page write operation, a 8 -a 16 should be the same or writes to an unknown address could occur. address a n d in = x t wc t oeh t oes a n a n ce we oe i/o 7 t dw d out = x d out = x x28c010, x28ht010
15 fn8105.1 february 12, 2007 toggle bit timing diagram note: 8. polling operations are by definit ion read cycles and are therefor e subject to read cycle timings. ce oe we i/o 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary. x28c010, x28ht010
16 fn8105.1 february 12, 2007 x28c010, x28ht010 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f32.6 mil-std-1835 gdip1-t32 (d-16, configuration a) 32 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.690 - 42.95 5 e 0.500 0.610 12.70 15.49 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 105 90 105 - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n32 328 rev. 0 8/06
17 fn8105.1 february 12, 2007 packaging information 32-lead ceramic flat pack type f note: all dimensions in inches (in parentheses in millimeters) 0.019 (0.48) 0.015 (0.38) 0.045 (1.14) max. pin 1 index 132 0.120 (3.05) 0.090 (2.29) min. 0.026 (0.66) 0.007 (0.18) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86) 0.830 (21.08) max. 0.050 (1.27) bsc 0.440 0.430 (10.93) 0.347 (8.82) 0.330 (8.38) 0.005 (0.13) min. 0.030 (0.76) min. 1.228 (31.19) 1.000 (25.40) x28c010, x28ht010
18 fn8105.1 february 12, 2007 packaging information 0.300 bsc 0.458 max. 0.450 0.008 pin 1 0.035 x 45 ref. 0.085 0.010 0.020 (1.02) x 45 ref. typ. (3) plcs. 0.050 bsc 0.400 bsc 0.708 max. 0.060/0.120 pin #1 index corner 1. all dimensions in inches (in parentheses in millimeters) 2. tolerance: 1% nlt0.005 (0.127) 0.700 0.010 0.005/0.015 0.025 0.003 0.050 0.005 0.006/0.022 detail a detail a 32-pad stretched ceramic leadless chip carrier package type n notes: x28c010, x28ht010
19 fn8105.1 february 12, 2007 packaging information 32-lead ceramic small outline gull wing package type r 1. all dimensions in inches 2. formed lead shall be planar with r espect to one another within 0.004 inches 0.340 0.007 see detail ?a? for lead information 0.440 max. 0.560 nom. 0.019 0.015 0.050 0.750 0.005 0.830 max. 0.060 nom. 0.020 min. 0.015 r typ. 0.035 min. 0.015 r typ. 0.035 typ. detail ?a? 0.560" typical 0.050" typical 0.050" typical footprint 0.030" typical 32 places 0.165 typ. notes: x28c010, x28ht010
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8105.1 february 12, 2007 packaging information 36 lead ceramic pin grid array package 15 17 19 21 22 14 16 18 20 23 10 9 27 28 8 7 29 30 5 2 36 34 32 4 3 1 35 33 typ. 0.100 (2.54) all leads pin 1 index note: leads 5, 14, 23, & 32 12 11 25 26 13 6 31 24 typ. 0.180 (.010) (4.57 .25) 4 corners 0.770 (19.56) 0.750 (19.05) sq a a 0.185 (4.70) 0.175 (4.45) 0.020 (0.51) 0.016 (0.41) 0.072 (1.83) 0.062 (1.57) 0.120 (3.05) 0.100 (2.54) note: all dimensions in inch es (in parentheses in millimeters) typ. 0.180 (.010) (4.57 .25) 4 corners 0.050 (1.27) 0.008 (0.20) a a package code g36.760x760a x28c010, x28ht010
x28c010 printer friendly version 5v, byte alterable e 2 prom datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ x28c010d-12 active comm 32 ld cerdip n/a 72.22 x28c010d-15 active comm 32 ld cerdip n/a 70.00 x28c010di active ind 32 ld cerdip n/a x28c010di-12 active ind 32 ld cerdip n/a 74.99 x28c010di-15 active ind 32 ld cerdip n/a 72.22 x28c010di-15c7681 active ind 32 ld cerdip n/a 76.47 x28c010dm active mil 32 ld cerdip n/a x28c010dm-12 active mil 32 ld cerdip n/a x28c010dm-15 active mil 32 ld cerdip n/a x28c010dmb-12 active mil 32 ld cerdip n/a 96.35 x28c010dmb-12c7309 active mil 32 ld cerdip n/a x28c010dmb-12c7729 active mil 32 ld cerdip n/a x28c010dmb-15 active mil 32 ld cerdip n/a 90.94 x28c010dmb-15c7762 active mil 32 ld cerdip n/a 90.94 x28c010dmb-20 active mil 32 ld cerdip n/a 88.24 x28c010dmc7237 active mil 32 ld cerdip n/a 251.76 x28c010fi-12 active ind 32 ld flatpack n/a 397.22 x28c010fi-15 active ind 32 ld flatpack n/a 512.50 x28c010fi-15c1009 active ind 32 ld flatpack n/a x28c010fi-20 active ind 32 ld flatpack n/a 421.67 x28c010fm active mil 32 ld flatpack n/a x28c010fm-12 active mil 32 ld flatpack n/a x28c010fmb-12 active mil 32 ld flatpack n/a x28c010fmb-15 active mil 32 ld flatpack n/a 176.47 x28c010fmb-15c7619 active mil 32 ld flatpack n/a x28c010fmb-15c7808 active mil 32 ld flatpack n/a x28c010k-25 active comm 36 ld pga n/a x28c010km-12 active mil 36 ld pga n/a x28c010km-25 active mil 36 ld pga n/a x28c010km-25c7237 active mil 36 ld pga n/a x28c010kmb-12 active ind 36 ld pga n/a x28c010kmb-15 active mil 36 ld pga n/a
x28c010ri-12 active ind 32 ld flatpack n/a 136.50 x28c010ri-20 active ind 32 ld flatpack n/a 127.78 x28c010ri-20t1 active ind 32 ld flatpack t+r n/a 127.78 x28c010rm-15 active mil 32 ld flatpack n/a 393.79 x28c010rmb-25 active mil 32 ld flatpack n/a 491.36 x28c010w active comm n/a x28c010fi-25 inactive ind 32 ld flatpack n/a x28c010fm-15 inactive mil 32 ld flatpack n/a X28C010FM-15C7856 inactive mil 32 ld flatpack n/a x28c010fmb inactive mil 32 ld flatpack n/a x28c010fmb-20 inactive mil 32 ld flatpack n/a x28c010fmb-25 inactive mil 32 ld flatpack n/a x28c010nm-12 inactive mil 32 ld extended lcc n/a x28c010nm-15 inactive mil 32 ld extended lcc n/a x28c010nm-20 inactive mil 32 ld extended lcc n/a x28c010nm-25 inactive mil 32 ld extended lcc n/a x28c010nmb inactive mil 32 ld extended lcc n/a x28c010nmb-12 inactive mil 32 ld extended lcc n/a x28c010nmb-15 inactive mil 32 ld extended lcc n/a x28c010nmb-15c7309 inactive mil 32 ld extended lcc n/a the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the intersil x28c010/x28ht010 is a 128k x 8 eeprom, fabricated with intersil's proprietary, high performance, floating gate cmos technology. like all intersil programmable non-volatile memories, the x28c010/x28ht010 is a 5v only device. the x28c010/x28ht010 features the jedec approved pin out for byte-wide memories, compatible with industry standard eeproms. the x28c010/x28ht010 supports a 256-byte page write operation, effectively providing a 19 s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. the x28c010/x28ht010 also features data polling and toggle bit polling, system software support schemes used to indicate the early completion of a write cycle. in addition, the x28c010/x28ht010 supports software data protection option. intersil eeproms are designed and tested for applications requiring extended endurance. data retention is specified to be greater than 100 years. key f eatures access time: 120ns simple byte and page write single 5v supply no external high voltages or v pp control circuits self-timed no erase before write no complex programming algorithms no overerase problem low power cmos active: 50ma standby: 500 a software data protection protects data against system level inadvertent writes high speed page write capability highly reliable direct write? cell endurance: 100,000 write cycles data retention: 100 years early end of write detection
data polling toggle bit polling x28ht010 is fuly functional @ +175c related documentation datasheet(s): 5v, byte alterable e 2 prom technical homepage: digital ics parametric data organization 128kx8-bit access time (ns) 120 active current max. (ma) 50 standby current max. ( a) 500 related devices parametric table x28c512 5v, byte alterable eeprom x28c513 5v, byte alterable eeprom x28hc256 256k, 32k x 8 bit; 5 volt, byte alterable eeprom x28hc64 64k, 8k x 8 bit; 5 volt, byte alterable eeprom about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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